1. Field of the Invention
The present invention generally relates to a converter apparatus (TDC apparatus), and more particularly, to a time-to-digital converter apparatus.
2. Description of Related Art
Thanks for the success and the development of integrated circuit (IC), a number of troublesome jobs to be done in the past can be fulfilled by using ICs today, wherein the job of measuring time is a good example. In the past, in order to accurately measure time length, people worried out to conceive and design few equipments. The time was effectively measured by using the equipments in association with appropriate algorithms. The conventional approach to measure time has the disadvantages of low measurement accuracy and high cost. In particular, the conventional approaches are not competent for measuring time in high speed (for example, an nano-second level measurement is required).
FIG. 1 is a diagram of a conventional TDC apparatus. Referring to FIG. 1, the TDC apparatus is for detecting the pulse-width in low-level of a pulse input signal T1, wherein a transistor BT1 and another transistor BT2 respectively receive and detect the pulse input signal T1 and the inverted signal T2 of the pulse input signal T1. When the pulse input signal T2 takes a low-level, the switch SW is enabled, and meanwhile a capacitor CA1 is pre-charged; when the pulse input signal T2 takes a high-level, the transistor BT2 is turned on and the switch SW is disabled, and meanwhile a current source I1 makes the capacitor CA1 discharged. The discharging voltage is transmitted to an analog-to-digital converter (ADC) 120 through a buffer 110 to produce a digital signal OUT, so that the digital value corresponding to the low-level pulse-width of the pulse input signal T1 is obtained.
FIG. 2 is a diagram of a conventional bi-slope TDC apparatus. The TDC apparatus in FIG. 2 employs two TDC apparatuses of FIG. 1 and has two input terminals for respectively receiving and detecting the pulse input signal T1 and the opposite pulse input signal T2, wherein the capacitor C2 has a greater capacitance than that of the capacitor C1, and the current source I2 is less than the current source I1. In the prior art, the output voltage V1 has a different discharging slope from that of the output voltage V2, and a comparator COMP1 is used to compare the two discharging slopes. Further, an AND-gate AN1 and a counter 201 are used so as to convert the comparison result into the digital signal OUT in association with a clock signal SCLK.
FIG. 3 is a diagram of a conventional TDC apparatus with a two-level time detect circuit (TDC). The circuit architecture is presented by the IEEE (Institute of Electrical and Electronic Engineers) paper “A High-Precision Time-to-Digital Converter Using a Two-level Conversion Scheme”, the Nuclear Science Periodic Vol. 51, No. 4 in August 2004.
The conventional circuit architecture herein employs a multi-phase detector 310 and the delay value VBNF produced by the double delay phase-locked loop 330 to detect and determine whether the integer multiple P is the pulse input signal Input over the delay value VBNF. The Vernier detector 320 is used to detect the remainder Input1 of the pulse input signal after dividing the pulse input signal Input by the delay value. The Vernier detector 320 also uses the difference between another delay value VBNS produced by the double delay phase-locked loop 330 and the delay value VBNF to detect the remainder Input1 of the pulse input signal so as to obtain the relation of the integer multiple V of the remainder Input1 of the pulse input signal over the difference between the delay value VBNF and the delay value VBNS.